题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
reg [2:0] cnt;
reg clk1,clk2;

always@(posedge clk_in,negedge rst) begin
    if(rst == 1'b0) begin
        cnt <= 0;
    end
    else if(cnt == 5-1) begin
        cnt <= 0;
    end
    else cnt <= cnt +1;
end

always@(posedge clk_in,negedge rst) begin
    if(rst == 1'b0) begin
        clk1 <= 0;
    end
    else if(cnt == 0 | cnt == (5-1)/2) begin
        clk1 <= ~clk1;
    end
    else clk1 <= clk1;
end

assign clk_out5 = clk1 ;
//*************code***********//
endmodule