题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter S0=6'b000_001;
parameter S1=6'b000_010;
parameter S2=6'b000_100;
parameter S3=6'b001_000;
parameter S4=6'b010_000;
parameter S5=6'b100_000;

reg [5:0] cur_state,next_state;

always@(posedge clk or negedge rst)begin
	if(!rst)
		cur_state <= S0;
	else
		cur_state <= next_state;
end


//*************code***********//
always@(*)begin
	if(!rst)
		next_state = S0;
	else
		case(cur_state)
				S0	   : next_state = data? S1: S0;
                S1     : next_state = data? S1: S2;
                S2     : next_state = data? S3: S0;
                S3     : next_state = data? S4: S2;
                S4     : next_state = data? S5: S2;
                S5     : next_state = data? S1: S0;
                default: next_state = S0;
	endcase
end

always@(posedge clk or negedge rst)begin
	if(!rst)
		flag <= 0;
	else if(next_state==S5)
		flag <= 1;
	else
		flag <= 0;
end

endmodule