题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
	
	parameter st0 = 3'd0;
	parameter st1 = 3'd1;
	parameter st2 = 3'd2;
	parameter st3 = 3'd3;
	parameter st4 = 3'd4;
	parameter st5 = 3'd5;
	parameter st6 = 3'd6;
	parameter st7 = 3'd7;

	reg [2:0] st_cur;
	reg [2:0] st_next;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			st_cur <= st0;
		end
		else begin
			st_cur <= st_next;
		end
	end

	reg done;
	always@(*) begin
		if (!rst_n) begin
			st_next <= st0;
		end
		else begin
			case(data_valid)
				1:begin
					case(st_cur)
						st0: 
							case(data)
								0: begin st_next = st1; end
								1: begin st_next = st5; end
							endcase
						st1:
							case(data)
								1: begin st_next = st2; end
								0: begin st_next = st5; end
							endcase
						st2:
							case(data)
								1: begin st_next = st3; end
								0: begin st_next = st5; end
							endcase
						st3:
							case(data)
								0: begin st_next = st4; end
								1: begin st_next = st5; end
							endcase
						st4:
							case(data)
								0: begin st_next = st1; end
								1: begin st_next = st5; end
							endcase
						st5:
							case(data)
								0: begin st_next = st1; end
								1: begin st_next = st5; end
							endcase
						st6:
						  case(data)
								0: begin st_next = st1; end
								1: begin st_next = st6; end
						  endcase
					endcase
				end
				0:begin
					case(st_cur)
						st0: begin st_next = st6; end
						st1: begin st_next = st6; end
						st2: begin st_next = st6; end
						st3: begin st_next = st6; end
						st4: begin st_next = st6; end
						st5: begin st_next = st6; end
						st6: begin st_next = st6; end
					endcase
				end
			endcase
		end
	end

	always @(*) begin
		if(!rst_n) begin
			match = 0;
		end
		else if((st_cur == st4) ) begin
			match = 1;
		end
		else begin
			match = 0;
		end
	end


  
endmodule