题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
	
	reg [3:0] cnt;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cnt <= 0;
		end
		else if(valid_in) begin
			cnt <= cnt + 1'b1;
		end
	end


	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			valid_out <= 0;
		end
		else if(cnt == 5 || cnt == 10 || cnt == 15) begin
			valid_out <= 1;
		end
		else begin
			valid_out <= 0;
		end
	end

	reg [143:0] data_out_reg;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_out_reg <= 0;
		end
		else if(valid_in) begin
			data_out_reg <= {data_out_reg[119:0],data_in};
		end
		else begin
			data_out_reg <= data_out_reg;
		end
	end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_out <= 0;
		end
		else if(cnt == 5) begin
			data_out <= {data_out_reg[119:0],data_in[23:16]};
		end
		else if(cnt == 10) begin
			data_out <= {data_out_reg[111:0],data_in[23:8]};
		end
		else if(cnt == 15) begin
			data_out <= {data_out_reg[103:0],data_in[23:0]};
		end
		else begin
			data_out <= data_out;
		end
	end


	
endmodule