题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
//存3出2，先存1个，再输出2个
reg [1:0]cnt;
reg [7:0]data_lock;
always@(posedge clk or negedge rst_n)begin
	if(~rst_n)begin	
		cnt <= 0;
	end
	else if(valid_in)begin
		if(cnt == 2)begin
			cnt <= 0 ;
		end
		else begin
			cnt <= cnt + 1;
		end
	end
end 
always@(posedge clk or negedge rst_n)begin
	if(~rst_n)begin
		data_lock <= 0 ;
		data_out  <= 0 ;
	end
	else if(valid_in) begin
		if(cnt == 1)begin
			data_out <= {data_lock ,data_in[7:4]};
			data_lock[3:0] <= data_in[3:0];
		end
		else if(cnt == 2)begin
			data_out <= {data_lock[3:0],data_in};
		end
		else begin
			data_lock <= data_in ;
		end
	end
end

always@(posedge clk or negedge rst_n)begin
	if(~rst_n)begin
		valid_out <= 0 ;
	end
	else if(valid_in && (cnt == 1 || cnt == 2))
		valid_out <= 1 ;

	else 
		valid_out <= 0;
end

endmodule

思路和上一题是一样的，根据时序图输出要求来确定在哪里输出，是立即输出而不是缓存后输出