题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [2:0] cnt_in;
reg [5:0] data_out;

always  @(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			cnt_in <= 0;
		else if(ready_a && valid_a)
			cnt_in <= cnt_in == 3'd5? 3'd0 : cnt_in + 1'b1;  
	end

always @(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			data_out <= 0;
		else if(ready_a && valid_a)
			data_out <= {data_a , data_out[5:1]}; 
	end

always @(posedge clk or negedge rst_n)
	begin
		if(!rst_n)	begin
			valid_b <= 1'b0;
			data_b  <= 0;
		end	else if(ready_a && valid_a)	begin 
			valid_b <= cnt_in == 3'd5? 1'b1 : 1'b0; 
			data_b	<= cnt_in == 3'd5? {data_a , data_out[5:1]} : data_b;
		end else 
			valid_b <= 1'b0;
	end


always @(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			ready_a <= 1'b0;
		else 
			ready_a <= 1'b1;
	end
  

endmodule