题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
reg clk_out5_reg;
reg[2:0]cnt;
always@(posedge clk_in  or negedge rst)begin
    if(!rst)begin
        cnt<=0;
    end
    else if(cnt==3'd4) cnt<=0;
    else cnt<=cnt+1;
end
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        clk_out5_reg<=0;
    end
    else begin
        if(cnt==3'd0)clk_out5_reg<=~clk_out5_reg;//占空比为%40
        else if(cnt==3'd2)clk_out5_reg<=~clk_out5_reg;
        else clk_out5_reg<=clk_out5_reg;
    end
end
assign clk_out5=clk_out5_reg;
//*************code***********//
endmodule