题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
    input clk,
    input rst_n,
     
    input write_en,
    input [7:0]write_addr,
    input [3:0]write_data,
     
    input read_en,
    input [7:0]read_addr,
    output reg [3:0]read_data
);
reg [3:0] myram [7:0];
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        myram[0]<=0;
        myram[1]<=0;
        myram[2]<=0;
        myram[3]<=0;
        myram[4]<=0;
        myram[5]<=0;
        myram[6]<=0;
        myram[7]<=0;
    end
    else
        myram[write_addr]<=write_en? write_data:myram[write_addr];
 
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        read_data<=0;

    else
        read_data<= read_en? myram[read_addr]: read_data;
end
     
endmodule

呃，就八位的话，为什么大家一定要循环赋值呢，直接给一个初值不就好了吗？另外哈，题目了说了深度是8位，好多人估计也不懂为啥要搞一个256深度的ram。不过题目里给的addr确实有点浪费资源，对于8深度的ram给3位的地址变量就足够用了