题解 | #同步FIFO#

/*无需变量cnt，用waddr和raddr来进行判断*/
`timescale 1ns/1ns
/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  //深度对2取对数，得到地址的位宽。
	,input [WIDTH-1:0] wdata      	//数据写入
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  //深度对2取对数，得到地址的位宽。
	,output reg [WIDTH-1:0] rdata 		//数据输出
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output reg				wfull	,
	output reg				rempty	,
	output wire [WIDTH-1:0]	rdata
);

reg	[$clog2(DEPTH):0]	waddr	;
reg	[$clog2(DEPTH):0]	raddr	;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		waddr	<= 'd0;
	    raddr   <= 'd0;
	end
	else begin
		waddr	<= (winc&~wfull)?(waddr + 1'b1):waddr;
	    raddr   <= (rinc&~rempty)?(raddr+1'b1):raddr;
	end
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		wfull  	<= 1'b0;
		rempty  <= 1'b0;
	end
	else begin
		rempty	<= (waddr[$clog2(DEPTH)]==raddr[$clog2(DEPTH)])?(waddr==raddr):1'b0;
		wfull	<= (waddr[$clog2(DEPTH)]==raddr[$clog2(DEPTH)])?1'b0:(waddr[$clog2(DEPTH)-1:0]==raddr[$clog2(DEPTH)-1:0]);
	end
end

dual_port_RAM #(.DEPTH (DEPTH),
                .WIDTH (WIDTH))
dual_port_RAM (
    .wclk  (clk  ),
    .wenc  (winc ),
    .waddr (waddr[$clog2(DEPTH)-1:0]),
    .wdata (wdata),
    .rclk  (clk  ),
    .renc  (rinc ),
    .raddr (raddr[$clog2(DEPTH)-1:0]),
    .rdata (rdata)
);

endmodule