题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output match
	);

	reg [8:0] a_tem;
	reg match_f;
	reg match_b;
	
	always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
		begin 
			match_f <= 1'b0;
			match_b <= 1'b0;
			a_tem <= 9'b0;
		end
		else
		begin
			
			a_tem <= {a_tem[7:0], a};

			if (a_tem[8:6] == 3'b011)
				match_f <= 1'b1;
			else
				match_f <= 1'b0;

			if (a_tem[2:0] == 3'b110)
				match_b <= 1'b1;
			else
				match_b <= 1'b0;
		end
	end

	assign match = match_b && match_f;

endmodule