题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
parameter N = 7;
reg [3:0] cnt;
reg p_clk;
reg n_clk;


always @(posedge clk_in ,negedge rst) begin
    if (!rst) begin
        cnt <= 4'b1;
    end else if(cnt == N) begin
        cnt <= 4'b1;
    end else begin
        cnt <= cnt + 4'b1;
    end
end

always @(posedge clk_in ,negedge rst) begin
    if (!rst) begin
        p_clk <= 1'b0;
    end else if((cnt == (N+1)/2) || (cnt == N)) begin
        p_clk <= p_clk+1'b1;
    end else begin
        p_clk <= p_clk;
    end
end
always @(negedge clk_in ,negedge rst) begin
    if (!rst) begin
        n_clk <= 1'b0;
    end else if((cnt == (N+1)/2) || (cnt == N)) begin
        n_clk <= n_clk+1'b1;
    end else begin
        n_clk <= n_clk;
    end
end


assign clk_out7 = n_clk || p_clk;


//*************code***********//
endmodule