题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);

	reg [3:0] num;

	always @(posedge clk or negedge rst_n)//非常莫名其妙的testbench，哪有上升沿有效的判断信号。
        if (!rst_n)
            begin 
                number <= 4'd0;
            end
        else 
            begin  
                number <= num;
            end

	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			num<=0;
		else
			if(mode)
				if(num==4'd9)
					num<=0;
				else
					num<=num+1;
			else
				if(num==4'd0)
					num<=9;
				else
					num<=num-1;

	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			zero<=0;
		else
			if((num==4'd0))
				zero<=1;
			else
				zero<=0;


endmodule

//非常莫名其妙的testbench，哪有上升沿有效的判断信号。