题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);
// Mealy型：输出信号不仅取决于当前状态，还取决于输入；
// Moore型：输出信号只取决于当前状态；
reg [2:0]crt_state,nxt_state;
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
//三段式
always@(posedge clk or negedge rst_n)
  if(!rst_n)
    crt_state <= s0;
  else
    crt_state <= nxt_state;
	
//这个组合逻辑块会在任何参与运算的信号（crt_state、din、rst_n等）发生变化时就重新计算nxt_state的值，以保证其能实时反映状态的转换条件。
//第二段always块通常是纯组合逻辑，用于根据当前状态以及输入信号等去计算下一个状态nxt_state,所以用always@(*)来对相关信号敏感保证实时响应输入变化进行计算。
always@(*) 
   if(!rst_n)
     nxt_state <= s0;
    else begin
        case(crt_state)
        s0:begin
            if(din) nxt_state <= s1;
            else    nxt_state <= s0;
        end
        s1:begin
            if(din) nxt_state <= s2;
            else    nxt_state <= s0;
        end
        s2:begin
            if(~din) nxt_state <= s3;
            else    nxt_state <= s2;
        end
        s3:begin
            if(din) nxt_state <= s4;
            else    nxt_state <= s0;
        end
        s4:begin
            if(din) nxt_state <= s1;
            else    nxt_state <= s0;
        end
        default: nxt_state <= s0;
        endcase
    end

always@(posedge clk or negedge rst_n)
  if(!rst_n)
    Y <= 0;
  else if(crt_state==s4)
    Y <= 1;
  else 
    Y <= 0;

endmodule