题解 | 根据状态转移图实现时序电路

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;


reg Y_reg;
reg [1:0] current_state;
reg [1:0] next_state;
assign Y = Y_reg;

always@(posedge clk or negedge rst_n)
if(!rst_n)begin
    current_state <=  S0;
    Y_reg <= 0;
end
else begin
    current_state <=  next_state;
end


// 状态转移逻辑
always @(*) begin
    case (current_state)
        S0: next_state = (C) ? S1 : S0;
        S1: next_state = (C) ? S1 : S3;
        S2: next_state = (C) ? S2 : S0;
        S3: next_state = (C) ? S2 : S3;
        default: next_state = S0;
    endcase
end

// 输出逻辑
always @(*) begin
    case (current_state)
        S0: Y_reg = 0;
        S1: Y_reg = 0;
        S2: Y_reg = (C) ? 1 : 0;
        S3: Y_reg = 1;
        default: Y_reg = 0;
    endcase
end



endmodule