题解 | 非整数倍数据位宽转换24to128

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
//24/128=3/16-->16个data_in才能组成3个data_out
//设置一个寄存器，处理一下衔接部分
reg [119:0] data_in_reg;
reg [3:0] data_cnt;//计数一下
always@(posedge clk or negedge rst_n)
if(!rst_n)
  data_cnt <= 0;
else if(valid_in)
  data_cnt <= data_cnt +1'b1;

//我图方便，把三个信号都一起写了，可分开写
always@(posedge clk or negedge rst_n)
if(!rst_n) begin
  data_in_reg <= 0;
  data_out <=0;
  valid_out <= 0;
end
else if(valid_in) begin
if(data_cnt == 4'd5) begin
  data_in_reg <= {data_in_reg[119:16],data_in[15:0]};
  data_out <= {data_in_reg,data_in[23:16]};
  valid_out <= 1;
end
else if(data_cnt == 4'd10) begin
  data_in_reg <= {data_in_reg[119:8],data_in[7:0]};
  data_out <= {data_in_reg[111:0],data_in[23:8]};
  valid_out <= 1;
end
else if(data_cnt == 4'd15) begin
  data_in_reg <= {data_in_reg,data_in};
  data_out <= {data_in_reg[103:0],data_in[23:0]};
  valid_out <= 1;
end
else begin
  data_in_reg <= {data_in_reg[95:0],data_in};//左移，先到的数据在高位
  valid_out <= 0;
end
end
else
  valid_out <= 0;
endmodule

位宽转换，核心就是移位寄存器寄存，然后计数器计数，计数到需要的位宽，输出即可