题解 | 信号发生器

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);

reg [4:0]	cnt ;
reg flag0 ;
reg flag3;

//方波计数器
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
	cnt <= 5'd0;
end
else if(wave_choise==1'b0)begin//模式为0，进行计数器的计数
if(cnt == 5'd19)begin
	cnt <= 5'd0;
end
else begin
	cnt <= cnt + 5'd1;
end
end
else begin
	cnt <= 5'd0;
end


//锯齿波标志寄存器
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
	flag3 <= 1'b0;
end
else if(wave_choise==2'd2)begin
	if(wave==5'd1)
	flag3 <= 1'b1;//锯齿波翻转标志
	else if(wave==5'd19)
	flag3 <= 1'b0;
end
else begin
	flag3 <= 1'b0;
end


always@(posedge clk or negedge rst_n)
if(!rst_n)begin
	wave <= 2'd0;
end
else begin
case(wave_choise)
	2'd0:begin 
		if (cnt == 5'd9)begin 
			wave <= 5'd20;
		end
		else if (cnt == 5'd19)begin 
			wave <= 5'd0;
		end
		end
	2'd1:begin wave <= (wave == 5'd20)?0:wave+1;end
	2'd2:begin wave <= (flag3==0)?wave-1:wave+1;end
	default: wave <= 0;
endcase
end

  
endmodule