题解 | RAM的简单实现

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
//从图中可以看出是伪双端口RAM
parameter DEPTH = 256;
parameter WIDTH = 4;
reg [WIDTH-1:0] FRAM [DEPTH-1:0];

always@(posedge clk) begin
 // FRAM[write_addr] <= write_en ? write_data : FRAM[write_addr];//这么写会出现乱码
//因为write_en=0的时候，不知道该存储什么数据。

  FRAM[write_addr] <= write_en ? write_data : 0;
  read_data <= read_en ? FRAM[read_addr] : 0;
end

endmodule

`timescale 1ns/1ns
module testbench();
	reg a;
	reg clk,rst_n;
	reg write_en;
	reg [7:0] write_addr;
	reg [3:0] write_data;
	reg read_en;
	reg [7:0] read_addr;
	wire [3:0] read_data;
	wire rise,down;
always #1 clk = ~clk;
initial begin
	$dumpfile("out.vcd");
	$dumpvars(0,testbench);
   // 初始化信号
        clk = 0;
        rst_n = 0;
        write_en = 0;
        write_addr = 0;
        write_data = 0;
        read_en = 0;
        read_addr = 0;

        // 复位
        #2;
        rst_n = 1;

        // 写入操作
        write_en = 1;
        write_addr = 0;
        write_data = 1;
        #2;
        write_addr = 1;
        write_data = 2;
        #2;
        write_addr = 2;
        write_data = 4;
        #2;
        write_en = 0;
        write_addr = 3;
        write_data = 6;
        #2;
        write_en = 1;
        write_addr = 4;
        write_data = 8;
        #2;
        write_addr = 5;
        write_data = 10;
        #2;
        write_en = 0;
        write_addr = 6;
        write_data = 12;
        #2;
        write_en = 1;
        write_addr = 7;
        write_data = 14;
      
      // 读取操作
        #2;
        read_en = 1;
        read_addr = 0;
        #2;
        read_addr = 1;
        #2;
        read_addr = 2;
        #2;
        read_addr = 3;
        #2;
        read_addr = 4;
        #2;
        read_addr = 5;
        #2;
        read_addr = 6;
        #2;
        read_addr = 7;
        #2;
        read_en = 0;

        #10;
        $finish;
    
end

ram_mod dut(
	.clk(clk),
	.rst_n(rst_n),
	.write_en(write_en),
	.write_addr(write_addr),
	.write_data(write_data),
	.read_en(read_en),
	.read_addr(read_addr),
	.read_data(read_data)
);

endmodule

FRAM[write_addr] <= write_en ? write_data : 0; 当write_en=0的时候，也得给FRAM一个数去存储

FRAM[write_addr] <= write_en ? write_data : FRAM[write_addr]; 这么写会出现下面的乱码