题解 | 不重叠序列检测

//不重叠序列检测,舍去之前结果
`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match, // Match output
    output reg not_match // Not match output
	);

    reg [5:0] reg_a;
    reg [2:0] cnt;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            reg_a <= 'b0; // Reset the register
            cnt <= 3'b0; // Reset the counter
        end else begin
            reg_a <= {reg_a[5:0], data}; // Shift in the new bit 'a'
            if (cnt < 3'd6) begin
                cnt <= cnt + 1; // Increment the counter until it reaches 7
            end else begin
                cnt <= 3'b1; // Keep the counter at 7 after reaching it
            end
        end
    end

always @(*) begin
        if (!rst_n) begin
            match <= 1'b0;
            not_match <= 1'b0; // Initialize not_match flag
        end else if(reg_a == 6'b011100 && cnt == 'd6)begin      //左边高位，右边低位
            match <= 1'b1; // Match found for the sequence "011xxx001"
            not_match <= 1'b0; // Reset not_match flag
        end else if(reg_a != 6'b011100 && cnt == 'd6)begin
            match <= 1'b0; // No match
            not_match <= 1'b1; // Set not_match flag
        end else begin
            match <= 1'b0; // No match
            not_match <= 1'b0; // Set not_match flag
        end
    end

endmodule