`timescale 1ns/1ns module fsm2( input wire clk , input wire rst , input wire data , output reg flag ); //*************code***********// parameter s0=0,s1=1,s2=2,s3=3,s4=4; reg [2:0]state,next_state; always @(posedge clk or negedge rst) begin if(~rst) state <= s0; else state <= next_state; end ...