题解 | 简易秒表

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
always@(posedge clk or negedge rst_n)
if(!rst_n)
  second <= 0;
else if(second==6'd60)
  second <= 6'd1;
else if(minute==6'd60)
  second <= 0;
else
  second <= second + 1;

always@(posedge clk or negedge rst_n)
if(!rst_n)
  minute <= 0;
else if(second==6'd60)
  minute <= minute + 1;
else if(minute==6'd60)
  minute <= 0;
	
	
endmodule

`timescale 1ns/1ns

module testbench();

	reg clk,rst_n;

	wire [5:0]second;
	wire [5:0]minute;
always #1 clk = ~clk;	
initial begin
	$dumpfile("out.vcd");
	$dumpvars(0,testbench);
	clk = 0;
	rst_n = 0;
    #3 rst_n=1;
	#180;
	$finish;
end


count_module dut(
	.clk(clk),
	.rst_n(rst_n),
	.second(second),
	.minute(minute)
);
endmodule